Removed plib dependency for PIC32.
This commit is contained in:
Janez
parent
8d0420b432
commit
40f329d0f1
5 changed files with 54 additions and 29 deletions
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@ -165,6 +165,7 @@ CO_ReturnError_t CO_CANmodule_init(
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CANmsgBuffDMApage = __builtin_dmapage(&CO_CAN1msg[0]);
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#endif
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}
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#if CO_CAN2msgBuffSize > 0
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else if(CANbaseAddress == ADDR_CAN2) {
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DMArxBaseAddress = CO_CAN2_DMA0;
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DMAtxBaseAddress = CO_CAN2_DMA1;
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@ -175,6 +176,7 @@ CO_ReturnError_t CO_CANmodule_init(
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CANmsgBuffDMApage = __builtin_dmapage(&CO_CAN2msg[0]);
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#endif
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}
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#endif
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else {
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return CO_ERROR_ILLEGAL_ARGUMENT;
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}
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@ -49,7 +49,7 @@
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#define CO_CAN1msgBuffSize 8
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#endif
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#ifndef CO_CAN2msgBuffSize
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#define CO_CAN2msgBuffSize 8
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#define CO_CAN2msgBuffSize 0 //CAN module 2 not used by default
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#endif
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@ -140,7 +140,7 @@ CO_ReturnError_t CO_CANmodule_init(
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/* Configure FIFO */
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CAN_REG(CANbaseAddress, C_FIFOBA) = KVA_TO_PA(CANmodule->CANmsgBuff);/* FIFO base address */
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CAN_REG(CANbaseAddress, C_FIFOBA) = CO_KVA_TO_PA(CANmodule->CANmsgBuff);/* FIFO base address */
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CAN_REG(CANbaseAddress, C_FIFOCON) = 0x001F0000; /* FIFO0: receive FIFO, 32 buffers */
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CAN_REG(CANbaseAddress, C_FIFOCON+0x40) = 0x00000080;/* FIFO1: transmit FIFO, 1 buffer */
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@ -343,7 +343,7 @@ CO_ReturnError_t CO_CANsend(CO_CANmodule_t *CANmodule, CO_CANtx_t *buffer){
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uint16_t addr = CANmodule->CANbaseAddress;
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volatile uint32_t* TX_FIFOcon = &CAN_REG(addr, C_FIFOCON+0x40);
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volatile uint32_t* TX_FIFOconSet = &CAN_REG(addr, C_FIFOCON+0x48);
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uint32_t* TXmsgBuffer = PA_TO_KVA1(CAN_REG(addr, C_FIFOUA+0x40));
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uint32_t* TXmsgBuffer = CO_PA_TO_KVA1(CAN_REG(addr, C_FIFOUA+0x40));
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uint32_t* message = (uint32_t*) buffer;
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uint32_t TX_FIFOconCopy;
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@ -494,7 +494,7 @@ void CO_CANinterrupt(CO_CANmodule_t *CANmodule){
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CO_CANrx_t *buffer = NULL; /* receive message buffer from CO_CANmodule_t object. */
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bool_t msgMatched = false;
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rcvMsg = (CO_CANrxMsg_t*) PA_TO_KVA1(CAN_REG(CANmodule->CANbaseAddress, C_FIFOUA));
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rcvMsg = (CO_CANrxMsg_t*) CO_PA_TO_KVA1(CAN_REG(CANmodule->CANbaseAddress, C_FIFOUA));
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rcvMsgIdent = rcvMsg->ident;
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if(rcvMsg->RTR) rcvMsgIdent |= 0x0800;
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if(CANmodule->useCANrxFilters){
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@ -553,7 +553,7 @@ void CO_CANinterrupt(CO_CANmodule_t *CANmodule){
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/* Copy message to CAN buffer */
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CANmodule->bufferInhibitFlag = buffer->syncFlag;
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uint32_t* TXmsgBuffer = PA_TO_KVA1(CAN_REG(CANmodule->CANbaseAddress, C_FIFOUA+0x40));
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uint32_t* TXmsgBuffer = CO_PA_TO_KVA1(CAN_REG(CANmodule->CANbaseAddress, C_FIFOUA+0x40));
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uint32_t* message = (uint32_t*) buffer;
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volatile uint32_t* TX_FIFOconSet = &CAN_REG(CANmodule->CANbaseAddress, C_FIFOCON+0x48);
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*(TXmsgBuffer++) = *(message++);
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@ -32,7 +32,6 @@
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#include <p32xxxx.h> /* processor header file */
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#include <plib.h>
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#include <stddef.h> /* for 'NULL' */
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#include <stdint.h> /* for 'int8_t' to 'uint64_t' */
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#include <stdbool.h> /* for true and false */
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@ -43,16 +42,25 @@
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#define ADDR_CAN2 (_CAN2_BASE_ADDRESS - _CAN1_BASE_ADDRESS)
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/* Translate a kernel virtual address in KSEG0 or KSEG1 to a real
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* physical address and back. */
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typedef unsigned long CO_paddr_t; /* a physical address */
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typedef unsigned long CO_vaddr_t; /* a virtual address */
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#define CO_KVA_TO_PA(v) ((CO_paddr_t)(v) & 0x1fffffff)
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#define CO_PA_TO_KVA0(pa) ((void *) ((pa) | 0x80000000))
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#define CO_PA_TO_KVA1(pa) ((void *) ((pa) | 0xa0000000))
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/* Critical sections */
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extern unsigned int CO_interruptStatus;
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#define CO_LOCK_CAN_SEND() CO_interruptStatus = INTDisableInterrupts()
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#define CO_UNLOCK_CAN_SEND() INTRestoreInterrupts(CO_interruptStatus)
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#define CO_LOCK_CAN_SEND() CO_interruptStatus = __builtin_disable_interrupts()
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#define CO_UNLOCK_CAN_SEND() if(CO_interruptStatus & 0x00000001) {__builtin_enable_interrupts();}
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#define CO_LOCK_EMCY() CO_interruptStatus = INTDisableInterrupts()
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#define CO_UNLOCK_EMCY() INTRestoreInterrupts(CO_interruptStatus)
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#define CO_LOCK_EMCY() CO_interruptStatus = __builtin_disable_interrupts()
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#define CO_UNLOCK_EMCY() if(CO_interruptStatus & 0x00000001) {__builtin_enable_interrupts();}
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#define CO_LOCK_OD() CO_interruptStatus = INTDisableInterrupts()
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#define CO_UNLOCK_OD() INTRestoreInterrupts(CO_interruptStatus)
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#define CO_LOCK_OD() CO_interruptStatus = __builtin_disable_interrupts()
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#define CO_UNLOCK_OD() if(CO_interruptStatus & 0x00000001) {__builtin_enable_interrupts();}
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/* Data types */
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@ -33,6 +33,8 @@
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#ifdef USE_EEPROM
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#include "eeprom.h" /* 25LC128 eeprom chip connected to SPI2A port. */
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#endif
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#include <xc.h> /* for interrupts */
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#include <sys/attribs.h> /* for interrupts */
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/* Configuration bits */
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@ -59,7 +61,11 @@
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#pragma config CP = OFF /* Code Protect Enable */
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#pragma config BWP = ON /* Boot Flash Write Protect */
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#pragma config PWP = PWP256K /* Program Flash Write Protect */
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#ifdef CO_ICS_PGx1
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#pragma config ICESEL = ICS_PGx1 /* ICE/ICD Comm Channel Select */
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#else
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#pragma config ICESEL = ICS_PGx2 /* ICE/ICD Comm Channel Select (2 for Explorer16 board) */
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#endif
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#pragma config DEBUG = ON /* Background Debugger Enable */
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@ -71,16 +77,17 @@
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#define CO_TMR_ISR_PRIORITY IPC2bits.T2IP /* Interrupt Priority */
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#define CO_TMR_ISR_ENABLE IEC0bits.T2IE /* Interrupt Enable bit */
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#define CO_CAN_ISR() void __ISR(_CAN_1_VECTOR, ipl5SOFT) CO_CAN1InterruptHandler(void)
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#define CO_CAN_ISR() void __ISR(_CAN_1_VECTOR, IPL5SOFT) CO_CAN1InterruptHandler(void)
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#define CO_CAN_ISR_FLAG IFS1bits.CAN1IF /* Interrupt Flag bit */
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#define CO_CAN_ISR_PRIORITY IPC11bits.CAN1IP /* Interrupt Priority */
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#define CO_CAN_ISR_ENABLE IEC1bits.CAN1IE /* Interrupt Enable bit */
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#define CO_CAN_ISR2() void __ISR(_CAN_2_VECTOR, ipl5SOFT) CO_CAN2InterruptHandler(void)
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#define CO_CAN_ISR2() void __ISR(_CAN_2_VECTOR, IPL5SOFT) CO_CAN2InterruptHandler(void)
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#define CO_CAN_ISR2_FLAG IFS1bits.CAN2IF /* Interrupt Flag bit */
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#define CO_CAN_ISR2_PRIORITY IPC11bits.CAN2IP /* Interrupt Priority */
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#define CO_CAN_ISR2_ENABLE IEC1bits.CAN2IE /* Interrupt Enable bit */
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#define CO_clearWDT() (WDTCONSET = _WDTCON_WDTCLR_MASK)
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/* Global variables and objects */
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volatile uint16_t CO_timer1ms = 0U; /* variable increments each millisecond */
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@ -92,12 +99,15 @@
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/* main ***********************************************************************/
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int main (void){
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unsigned int temp_ui;
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CO_NMT_reset_cmd_t reset = CO_RESET_NOT;
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/* Configure system for maximum performance and enable multi vector interrupts. */
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SYSTEMConfig(CO_FSYS*1000, SYS_CFG_WAIT_STATES | SYS_CFG_PCACHE);
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INTConfigureSystem(INT_SYSTEM_CONFIG_MULT_VECTOR);
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INTEnableInterrupts();
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/* Configure system for maximum performance. plib is necessary for that.*/
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/* SYSTEMConfig(CO_FSYS*1000, SYS_CFG_WAIT_STATES | SYS_CFG_PCACHE); */
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/* Enable system multi vectored interrupts */
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INTCONbits.MVEC = 1;
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__builtin_enable_interrupts();
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/* Disable JTAG and trace port */
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DDPCONbits.JTAGEN = 0;
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@ -105,9 +115,9 @@ int main (void){
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/* Verify, if OD structures have proper alignment of initial values */
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if(CO_OD_RAM.FirstWord != CO_OD_RAM.LastWord) while(1) ClearWDT();
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if(CO_OD_EEPROM.FirstWord != CO_OD_EEPROM.LastWord) while(1) ClearWDT();
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if(CO_OD_ROM.FirstWord != CO_OD_ROM.LastWord) while(1) ClearWDT();
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if(CO_OD_RAM.FirstWord != CO_OD_RAM.LastWord) while(1) CO_clearWDT();
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if(CO_OD_EEPROM.FirstWord != CO_OD_EEPROM.LastWord) while(1) CO_clearWDT();
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if(CO_OD_ROM.FirstWord != CO_OD_ROM.LastWord) while(1) CO_clearWDT();
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/* initialize EEPROM - part 1 */
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@ -141,11 +151,11 @@ int main (void){
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nodeId = OD_CANNodeID;
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if(nodeId<1 || nodeId>127) nodeId = 0x10;
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CANBitRate = OD_CANBitRate;/* in kbps */
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/* initialize CANopen */
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err = CO_init(ADDR_CAN1, nodeId, CANBitRate);
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if(err != CO_ERROR_NO){
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while(1) ClearWDT();
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while(1) CO_clearWDT();
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/* CO_errorReport(CO->em, CO_EM_MEMORY_ALLOCATION_ERROR, CO_EMC_SOFTWARE_INTERNAL, err); */
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}
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@ -200,7 +210,7 @@ int main (void){
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/* loop for normal program execution ******************************************/
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uint16_t timer1msCopy, timer1msDiff;
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ClearWDT();
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CO_clearWDT();
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/* calculate cycle time for performance measurement */
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@ -227,13 +237,13 @@ int main (void){
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/* Application asynchronous program */
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programAsync(timer1msDiff);
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ClearWDT();
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CO_clearWDT();
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/* CANopen process */
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reset = CO_process(CO, timer1msDiff, NULL);
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ClearWDT();
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CO_clearWDT();
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#ifdef USE_EEPROM
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@ -251,13 +261,18 @@ int main (void){
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CO_delete(ADDR_CAN1);
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/* reset */
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SoftReset();
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SYSKEY = 0x00000000;
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SYSKEY = 0xAA996655;
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SYSKEY = 0x556699AA;
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RSWRSTSET = 1;
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temp_ui = RSWRST;
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while(1);
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}
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/* timer interrupt function executes every millisecond ************************/
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#ifndef USE_EXTERNAL_TIMER_1MS_INTERRUPT
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void __ISR(_TIMER_2_VECTOR, ipl3SOFT) CO_TimerInterruptHandler(void){
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void __ISR(_TIMER_2_VECTOR, IPL3SOFT) CO_TimerInterruptHandler(void){
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bool_t syncWas;
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CO_TMR_ISR_FLAG = 0;
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@ -272,7 +287,7 @@ void __ISR(_TIMER_2_VECTOR, ipl3SOFT) CO_TimerInterruptHandler(void){
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/* Re-enable CANrx, if it was disabled by SYNC callback */
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// TODO this and outer loop
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/* Further I/O or nonblocking application code may go here. */
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program1ms();
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