diff --git a/stack/PIC24_dsPIC33/CO_driver.c b/stack/PIC24_dsPIC33/CO_driver.c index feb9235..f6ed956 100644 --- a/stack/PIC24_dsPIC33/CO_driver.c +++ b/stack/PIC24_dsPIC33/CO_driver.c @@ -165,6 +165,7 @@ CO_ReturnError_t CO_CANmodule_init( CANmsgBuffDMApage = __builtin_dmapage(&CO_CAN1msg[0]); #endif } +#if CO_CAN2msgBuffSize > 0 else if(CANbaseAddress == ADDR_CAN2) { DMArxBaseAddress = CO_CAN2_DMA0; DMAtxBaseAddress = CO_CAN2_DMA1; @@ -175,6 +176,7 @@ CO_ReturnError_t CO_CANmodule_init( CANmsgBuffDMApage = __builtin_dmapage(&CO_CAN2msg[0]); #endif } +#endif else { return CO_ERROR_ILLEGAL_ARGUMENT; } diff --git a/stack/PIC24_dsPIC33/CO_driver.h b/stack/PIC24_dsPIC33/CO_driver.h index e350e24..a007b4c 100644 --- a/stack/PIC24_dsPIC33/CO_driver.h +++ b/stack/PIC24_dsPIC33/CO_driver.h @@ -49,7 +49,7 @@ #define CO_CAN1msgBuffSize 8 #endif #ifndef CO_CAN2msgBuffSize - #define CO_CAN2msgBuffSize 8 + #define CO_CAN2msgBuffSize 0 //CAN module 2 not used by default #endif diff --git a/stack/PIC32/CO_driver.c b/stack/PIC32/CO_driver.c index 9513f73..ebb3689 100644 --- a/stack/PIC32/CO_driver.c +++ b/stack/PIC32/CO_driver.c @@ -140,7 +140,7 @@ CO_ReturnError_t CO_CANmodule_init( /* Configure FIFO */ - CAN_REG(CANbaseAddress, C_FIFOBA) = KVA_TO_PA(CANmodule->CANmsgBuff);/* FIFO base address */ + CAN_REG(CANbaseAddress, C_FIFOBA) = CO_KVA_TO_PA(CANmodule->CANmsgBuff);/* FIFO base address */ CAN_REG(CANbaseAddress, C_FIFOCON) = 0x001F0000; /* FIFO0: receive FIFO, 32 buffers */ CAN_REG(CANbaseAddress, C_FIFOCON+0x40) = 0x00000080;/* FIFO1: transmit FIFO, 1 buffer */ @@ -343,7 +343,7 @@ CO_ReturnError_t CO_CANsend(CO_CANmodule_t *CANmodule, CO_CANtx_t *buffer){ uint16_t addr = CANmodule->CANbaseAddress; volatile uint32_t* TX_FIFOcon = &CAN_REG(addr, C_FIFOCON+0x40); volatile uint32_t* TX_FIFOconSet = &CAN_REG(addr, C_FIFOCON+0x48); - uint32_t* TXmsgBuffer = PA_TO_KVA1(CAN_REG(addr, C_FIFOUA+0x40)); + uint32_t* TXmsgBuffer = CO_PA_TO_KVA1(CAN_REG(addr, C_FIFOUA+0x40)); uint32_t* message = (uint32_t*) buffer; uint32_t TX_FIFOconCopy; @@ -494,7 +494,7 @@ void CO_CANinterrupt(CO_CANmodule_t *CANmodule){ CO_CANrx_t *buffer = NULL; /* receive message buffer from CO_CANmodule_t object. */ bool_t msgMatched = false; - rcvMsg = (CO_CANrxMsg_t*) PA_TO_KVA1(CAN_REG(CANmodule->CANbaseAddress, C_FIFOUA)); + rcvMsg = (CO_CANrxMsg_t*) CO_PA_TO_KVA1(CAN_REG(CANmodule->CANbaseAddress, C_FIFOUA)); rcvMsgIdent = rcvMsg->ident; if(rcvMsg->RTR) rcvMsgIdent |= 0x0800; if(CANmodule->useCANrxFilters){ @@ -553,7 +553,7 @@ void CO_CANinterrupt(CO_CANmodule_t *CANmodule){ /* Copy message to CAN buffer */ CANmodule->bufferInhibitFlag = buffer->syncFlag; - uint32_t* TXmsgBuffer = PA_TO_KVA1(CAN_REG(CANmodule->CANbaseAddress, C_FIFOUA+0x40)); + uint32_t* TXmsgBuffer = CO_PA_TO_KVA1(CAN_REG(CANmodule->CANbaseAddress, C_FIFOUA+0x40)); uint32_t* message = (uint32_t*) buffer; volatile uint32_t* TX_FIFOconSet = &CAN_REG(CANmodule->CANbaseAddress, C_FIFOCON+0x48); *(TXmsgBuffer++) = *(message++); diff --git a/stack/PIC32/CO_driver.h b/stack/PIC32/CO_driver.h index b471007..cce3213 100644 --- a/stack/PIC32/CO_driver.h +++ b/stack/PIC32/CO_driver.h @@ -32,7 +32,6 @@ #include /* processor header file */ -#include #include /* for 'NULL' */ #include /* for 'int8_t' to 'uint64_t' */ #include /* for true and false */ @@ -43,16 +42,25 @@ #define ADDR_CAN2 (_CAN2_BASE_ADDRESS - _CAN1_BASE_ADDRESS) +/* Translate a kernel virtual address in KSEG0 or KSEG1 to a real + * physical address and back. */ + typedef unsigned long CO_paddr_t; /* a physical address */ + typedef unsigned long CO_vaddr_t; /* a virtual address */ + #define CO_KVA_TO_PA(v) ((CO_paddr_t)(v) & 0x1fffffff) + #define CO_PA_TO_KVA0(pa) ((void *) ((pa) | 0x80000000)) + #define CO_PA_TO_KVA1(pa) ((void *) ((pa) | 0xa0000000)) + + /* Critical sections */ extern unsigned int CO_interruptStatus; - #define CO_LOCK_CAN_SEND() CO_interruptStatus = INTDisableInterrupts() - #define CO_UNLOCK_CAN_SEND() INTRestoreInterrupts(CO_interruptStatus) + #define CO_LOCK_CAN_SEND() CO_interruptStatus = __builtin_disable_interrupts() + #define CO_UNLOCK_CAN_SEND() if(CO_interruptStatus & 0x00000001) {__builtin_enable_interrupts();} - #define CO_LOCK_EMCY() CO_interruptStatus = INTDisableInterrupts() - #define CO_UNLOCK_EMCY() INTRestoreInterrupts(CO_interruptStatus) + #define CO_LOCK_EMCY() CO_interruptStatus = __builtin_disable_interrupts() + #define CO_UNLOCK_EMCY() if(CO_interruptStatus & 0x00000001) {__builtin_enable_interrupts();} - #define CO_LOCK_OD() CO_interruptStatus = INTDisableInterrupts() - #define CO_UNLOCK_OD() INTRestoreInterrupts(CO_interruptStatus) + #define CO_LOCK_OD() CO_interruptStatus = __builtin_disable_interrupts() + #define CO_UNLOCK_OD() if(CO_interruptStatus & 0x00000001) {__builtin_enable_interrupts();} /* Data types */ diff --git a/stack/PIC32/main_PIC32.c b/stack/PIC32/main_PIC32.c index 576b9b2..b1ba951 100644 --- a/stack/PIC32/main_PIC32.c +++ b/stack/PIC32/main_PIC32.c @@ -33,6 +33,8 @@ #ifdef USE_EEPROM #include "eeprom.h" /* 25LC128 eeprom chip connected to SPI2A port. */ #endif +#include /* for interrupts */ +#include /* for interrupts */ /* Configuration bits */ @@ -59,7 +61,11 @@ #pragma config CP = OFF /* Code Protect Enable */ #pragma config BWP = ON /* Boot Flash Write Protect */ #pragma config PWP = PWP256K /* Program Flash Write Protect */ +#ifdef CO_ICS_PGx1 #pragma config ICESEL = ICS_PGx1 /* ICE/ICD Comm Channel Select */ +#else + #pragma config ICESEL = ICS_PGx2 /* ICE/ICD Comm Channel Select (2 for Explorer16 board) */ +#endif #pragma config DEBUG = ON /* Background Debugger Enable */ @@ -71,16 +77,17 @@ #define CO_TMR_ISR_PRIORITY IPC2bits.T2IP /* Interrupt Priority */ #define CO_TMR_ISR_ENABLE IEC0bits.T2IE /* Interrupt Enable bit */ - #define CO_CAN_ISR() void __ISR(_CAN_1_VECTOR, ipl5SOFT) CO_CAN1InterruptHandler(void) + #define CO_CAN_ISR() void __ISR(_CAN_1_VECTOR, IPL5SOFT) CO_CAN1InterruptHandler(void) #define CO_CAN_ISR_FLAG IFS1bits.CAN1IF /* Interrupt Flag bit */ #define CO_CAN_ISR_PRIORITY IPC11bits.CAN1IP /* Interrupt Priority */ #define CO_CAN_ISR_ENABLE IEC1bits.CAN1IE /* Interrupt Enable bit */ - #define CO_CAN_ISR2() void __ISR(_CAN_2_VECTOR, ipl5SOFT) CO_CAN2InterruptHandler(void) + #define CO_CAN_ISR2() void __ISR(_CAN_2_VECTOR, IPL5SOFT) CO_CAN2InterruptHandler(void) #define CO_CAN_ISR2_FLAG IFS1bits.CAN2IF /* Interrupt Flag bit */ #define CO_CAN_ISR2_PRIORITY IPC11bits.CAN2IP /* Interrupt Priority */ #define CO_CAN_ISR2_ENABLE IEC1bits.CAN2IE /* Interrupt Enable bit */ + #define CO_clearWDT() (WDTCONSET = _WDTCON_WDTCLR_MASK) /* Global variables and objects */ volatile uint16_t CO_timer1ms = 0U; /* variable increments each millisecond */ @@ -92,12 +99,15 @@ /* main ***********************************************************************/ int main (void){ + unsigned int temp_ui; CO_NMT_reset_cmd_t reset = CO_RESET_NOT; - /* Configure system for maximum performance and enable multi vector interrupts. */ - SYSTEMConfig(CO_FSYS*1000, SYS_CFG_WAIT_STATES | SYS_CFG_PCACHE); - INTConfigureSystem(INT_SYSTEM_CONFIG_MULT_VECTOR); - INTEnableInterrupts(); + /* Configure system for maximum performance. plib is necessary for that.*/ + /* SYSTEMConfig(CO_FSYS*1000, SYS_CFG_WAIT_STATES | SYS_CFG_PCACHE); */ + + /* Enable system multi vectored interrupts */ + INTCONbits.MVEC = 1; + __builtin_enable_interrupts(); /* Disable JTAG and trace port */ DDPCONbits.JTAGEN = 0; @@ -105,9 +115,9 @@ int main (void){ /* Verify, if OD structures have proper alignment of initial values */ - if(CO_OD_RAM.FirstWord != CO_OD_RAM.LastWord) while(1) ClearWDT(); - if(CO_OD_EEPROM.FirstWord != CO_OD_EEPROM.LastWord) while(1) ClearWDT(); - if(CO_OD_ROM.FirstWord != CO_OD_ROM.LastWord) while(1) ClearWDT(); + if(CO_OD_RAM.FirstWord != CO_OD_RAM.LastWord) while(1) CO_clearWDT(); + if(CO_OD_EEPROM.FirstWord != CO_OD_EEPROM.LastWord) while(1) CO_clearWDT(); + if(CO_OD_ROM.FirstWord != CO_OD_ROM.LastWord) while(1) CO_clearWDT(); /* initialize EEPROM - part 1 */ @@ -141,11 +151,11 @@ int main (void){ nodeId = OD_CANNodeID; if(nodeId<1 || nodeId>127) nodeId = 0x10; CANBitRate = OD_CANBitRate;/* in kbps */ - + /* initialize CANopen */ err = CO_init(ADDR_CAN1, nodeId, CANBitRate); if(err != CO_ERROR_NO){ - while(1) ClearWDT(); + while(1) CO_clearWDT(); /* CO_errorReport(CO->em, CO_EM_MEMORY_ALLOCATION_ERROR, CO_EMC_SOFTWARE_INTERNAL, err); */ } @@ -200,7 +210,7 @@ int main (void){ /* loop for normal program execution ******************************************/ uint16_t timer1msCopy, timer1msDiff; - ClearWDT(); + CO_clearWDT(); /* calculate cycle time for performance measurement */ @@ -227,13 +237,13 @@ int main (void){ /* Application asynchronous program */ programAsync(timer1msDiff); - ClearWDT(); + CO_clearWDT(); /* CANopen process */ reset = CO_process(CO, timer1msDiff, NULL); - ClearWDT(); + CO_clearWDT(); #ifdef USE_EEPROM @@ -251,13 +261,18 @@ int main (void){ CO_delete(ADDR_CAN1); /* reset */ - SoftReset(); + SYSKEY = 0x00000000; + SYSKEY = 0xAA996655; + SYSKEY = 0x556699AA; + RSWRSTSET = 1; + temp_ui = RSWRST; + while(1); } /* timer interrupt function executes every millisecond ************************/ #ifndef USE_EXTERNAL_TIMER_1MS_INTERRUPT -void __ISR(_TIMER_2_VECTOR, ipl3SOFT) CO_TimerInterruptHandler(void){ +void __ISR(_TIMER_2_VECTOR, IPL3SOFT) CO_TimerInterruptHandler(void){ bool_t syncWas; CO_TMR_ISR_FLAG = 0; @@ -272,7 +287,7 @@ void __ISR(_TIMER_2_VECTOR, ipl3SOFT) CO_TimerInterruptHandler(void){ /* Re-enable CANrx, if it was disabled by SYNC callback */ // TODO this and outer loop - + /* Further I/O or nonblocking application code may go here. */ program1ms();